In a dynamic random access memory (DRAM) device, the reading capacity of the memory cell can be increased and the soft error rate can be reduced by increasing the capacitance of the memory cell capacitor. Accordingly, increased capacitance for the memory cells can improve the performance of the memory device. As dynamic random access memory devices become more highly integrated, however, the surface area occupied by each memory cell is reduced thus reducing the area available for each memory cell capacitor. It is therefore desirable to maintain a predetermined capacitance for each memory cell capacitor as the space available for each memory cell capacitor is reduced.
There have been efforts to provide increased memory cell capacitance with memory cell capacitors occupying a reduced area of an integrated circuit substrate. In particular, there have been efforts to increase the surface area of a lower capacitor electrode. For example, polysilicon electrodes have been fabricated having fin structures, box structures, and cylindrical structures.
Design rule limitations, however, may make it difficult to gain satisfactory increases in the memory cell capacitance when using the electrode structures discussed above. In addition, the complicated manufacturing steps used to fabricate these three-dimensional structures may result in an increased soft error rate. Accordingly, there continues to exist a need in the art for improved memory cell capacitor structures.